Re: [NTLK] New accelerator idea. needs no crystal. Need Help.

From: Johannes Wolf (mp2100_at_mail-gw.estec.esa.nl)
Date: Wed Jul 10 2002 - 04:09:06 EDT


David,

thank you a lot for bringing us back to reality.
I have to admit that I have been a bit too enthusiastic and dreaming ...
And all those ideas were based on a total fog around the Newts circuit
diagram.
I was of course not aware that the voyager chips are driven directly from
the 3.68 MHz clock.
That changes the situation dramatically.
And it might be the case as well that the SA-110 from digital does not use
the multiplicator setting pins or that they are fixed (the documentation I
referred to was the intel one).
And you are absolutely right saying that the simplest modification is the
best one, I fully agree.

So the only thing left for me is to say to everybody: stay quiet and wait
until Mr. PCB man announces his solution. I am absolutely sure that it will
be a good and simple modification to our beloved Newt.
And you can count on the fact that I will be amongst the first ones who will
go for it.

Johannes

> -----Original Message-----
> From: newtontalk-bounce_at_newtontalk.net
> [mailto:newtontalk-bounce_at_newtontalk.net]On Behalf Of Humphreys, David
> (URB)
> Sent: Tuesday, July 09, 2002 6:46 PM
> To: 'newtontalk_at_newtontalk.net'
> Subject: Re: [NTLK] New accelerator idea. needs no crystal. Need Help.
>
>
> The point is not what is happening inside the SA-110, but its'
> relationship to things outside it. As DCLK and MCLK are
> PLL'ed, they will of corse have a fixed relationship.
> It is not this that I am referring to though. The 3.6864MHz (not
> 3.57 MHz) crystal drives the SA-110 and is multiplied
> up. It also drives the voyager chips directly.
> Just look and see that it connects to U6. If you change the PLL
> multiplier you change the SA-110's CCLK for sure but the
> frequency of the clock into U6 is still 3.6864MHz.
> Now you have destroyed the timing relationship between these chips.
>
> Just becase a device has the CAPIBILLITY to do certain things
> deosn't mean that it will implemented in all systems.
>
>
> >Since you can also control the ration between DCLK and MCLK
> (divide by 2 ..
> >9)by means of the MCCFG setting, the IO clock can also be adjusted.
>
> Yes, but in fixed steps that do not allow all posibillities.
>
> >And now we are back to the question why this was not done in the first
> >place:
> >acording to the manual there are certain selection types for certain max.
> >clock frequencies. It may be true that there was a financial
> aspect to chose
> >the lower performance selection types or to be absolutely sure, maybe a
> >power consumption aspect played a role as well ...
> >And in my opinion: when we all agreed that it is possible to
> overclock the
> >Newt "externally" why this should not work as well with changing the
> >settings for the PLL???
>
> Because changing the reference frequency ensures that all the
> rest of the system will follow until you reach the stops.
>
> >From an engineering point of view this would be the smartest
> solution, would
> >it not? But of course in the light of realization it is much
> more scary to
> >diconnect and reconnect single pins from the SA-110...
>
> No, it would not! Perhaps on the drawing board at the start of
> the project it could have been designed in but not as an
> afterthought and especially without full schematics.
> There are not too many people that would attempt this kind of
> modification. From an engineering point of view, simple is
> best. I have a solution that involves none of this nonsense,
> dosen't use a crystal and is controlled by software. I am
> still refining it and I am not ready to release it to the world
> yet, but when I do you can rest assured that it will be
> a simple mod.
>
> >I am looking forward to read your comment.
>
> >Johannes
>
> There it is.
>
> Regards,
>
> PCBman
>
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