[NTLK] Cache, L1~L3....

From: Jeffrey M. Swiger (N8NOE_at_comcast.net)
Date: Thu Dec 05 2002 - 11:05:08 EST


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Hi all;
        I alwas thought I was right when I'd say, YOU don't ask =
questions from=20
a Crazy Person, But yet again, I'm wrong...
I was asked about the L1, L2, L3 Cache of a system and I sent a letter,=20=

and I thought I'd Pass it to somepeople, Who
might ask the same thing. I find that some Commercial, or something=20
like that brought it up, and of-course didn't explain it.
This is how I get asked this stuff, But here is what I sent!... READ IT!

1) The L1 Cache - This is high speed SRAM found directly on the=20
microprocessor, allowing instructions to be held for calculations. To=20
conserve space and reduce cost, there is usually no more than 64=20
kilobytes on chip.

2) The L2 Cache - A secondary RAM area that operates at either the=20
motherboard bus clock speed, the microprocessor clock speed, or a=20
fraction of either. It holds used instructions or other data that will=20=

possibly be used again shortly. Most new PCs have between 128 KB- 1024=20=

KB (1 megabyte).

3) The L3 Cache - The third cache level, and also the least used. When=20=

the microprocessor and motherboard both have L2 caches, the motherboard=20=

cache is designated L3, since its further away. It provides much the=20
same role as the L2, but with a lower potential for performance gains.=20=

The few PCs that have an L3 cache usually have 512 KB of space=20
available.

4) The System RAM - The largest and slowest RAM area. It stores data=20
directly from storage devices to help the CPU keep up its speed.=20
Today's PCs have between 32-64 MB, with numbers skyrocketing from there=20=

depending on the user.

Does this help?...I was also talking about the Bottleneck, This will=20
also happen when your in a Hi-Processor mode. Disk Swap File/Gaming...

Eliminating data bottlenecks
Since much of the data being processed is in dedicated L3 cache,=20
there=92s less data traveling from the processor to main memory at any=20=

given time. This in turn means there=92s less data traffic in the system=20=

controller, and a lower instance of bottlenecks caused by multiple data=20=

streams contending for the system bus. This leaves more bandwidth for=20
dealing with data from other subsystems, such as AGP graphics, PCI or=20
the I/O controller.

                          *** N8NOE ***
                        Jeffrey M. Swiger
         G4/933 PowerMac (2002 QuickSilver)
           G4/800Mhz PowerMac CUBE
          G3/700 12" iBook (2002 Ice-Book)
                  MP2100 Apple Newton's

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 =20
                            =20=

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